1. Field of the Invention
The present invention relates to a dynamic logic circuit mounted on a CMOS semiconductor integrated circuit chip and a circuit included the dynamic logic circuit. In particular, the invention relates to a dynamic logic circuit operating at a high speed and a circuit including the dynamic logic circuit.
2. Description of the Related Art
FIG. 3 shows a prior art circuit disclosed in FIG. 4 of Japanese Patent Application No. 61-224623. FIG. 4 shows another prior art circuit disclosed in FIG. 7 of Japanese Patent Application No. 61-224623. Although in Japanese Patent Application No. 61-224623, both of FIGS. 4 or 7 show an example circuit having five input signal lines, to simplify them, FIGS. 3 and 4 show prior art circuits each having three input signal lines.
In the prior art circuit of FIG. 4, when a clock signal 160 is at a low level, because a P-channel type MOS transistor 100 is conducted and a N-channel type MOS transistor 400 is cut off, an internal signal 171 becomes a high level and an output signal 170 becomes a low level despite the status of input signals 151 and 153. This status is called a precharged status. Thereafter, when the clock signal 160 becomes a high level, the P-channel type MOS transistor 100 is cut off and the N-channel type MOS transistor 400 conducts. At this moment, when at least one of the input signals 151 through 153 is at a low level, the internal signal 171 becomes a floating status and is held at a high level and the output signal 170 is held at a low level. Further, when all of input signals 151 through 153 become a high level, the internal signal 171 becomes a low level and the output signal 170 becomes a high level because N-channel type MOS transistors 101 and 103 conduct. Accordingly, when at least one of input signals 151 through 153 is at a low level, an output signal becomes a low level and when all of the input signals 151 through 153 become a high level, then the output signal becomes a high level. In other words, the circuit in FIG. 4 is operated as a AND circuit.
However, in FIG. 4, when the input signals 151 through 153 becomes a high level and the internal signal 171 is in a high-to-low transition, a current flows through a series of four MOS transistor 103, 102, 101 and 400 despite only three input signals. Accordingly, there is a problem when a time taken from all of input signals being a high level to the internal signal 171 being in a low-to-high transition (and the output signal 170 being in a low-to-high transition) is longer than a time from when three MOS transistors are used.
FIG. 3 is a prior example circuit that improves the prior art circuit of FIG. 4. Although the circuit in FIG. 3 operates as an AND circuit just as the circuit in FIG. 4, when the input signals 151 through 153 become a high level and the internal signal 171 is in a high-to-low transition, a short period of time is allowed as compared with the circuit of FIG. 4 because a current flows through the three MOS transistors 103, 102 and 101.